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(Image courtesy of Intel).

Intel Adds to Advanced Packaging Arsenal

Intel is expanding its advanced packaging arsenal in an effort to reestablish its lead in chip manufacturing technology. Intel has introduced three new technologies for building chips out of smaller silicon die and boosting the bandwidth between them in a package. The announcements of co-EMIB, ODI and MDIO came ahead of the SemiCon West conference last week.

The company has started selling chips for data centers and personal computers assembled from slivers of siliconmore commonly called chiplets. These components include CPUs, GPUs and various other ICs with prepackaged functions, including analog, memory and power management. The chips communicate over interconnects installed in the package to act as though they share the same die.

Advanced packaging is playing a bigger and bigger role at Intel, the largest microprocessor maker in the world. Intel, which pumped $13.5 billion into research and development last year, said chiplets would enable it to deliver higher performance, lower power chips faster and more cheaply than today. Advanced packaging is basically a small-scale version of arranging discrete ICs on a PCB.

This is increasingly important as the Silicon Valley company contends with the slowdown in Moore's Law, which has served as the golden rule of the electronics industry for decades. Delays in developing its 10-nanometer production node have been a bad black eye for Intel. The company last year surrendered its chip-making lead to TSMC, which has started supplying 7-nanometer chips for AMD and other rivals.

The Santa Clara, California-based company sees packaging playing a key role in reasserting its dominance. Intel is painting a portrait of the future where it assembles chips from interchangeable ICs instead of cramming all the same parts into a self-contained system-on-chip (SoC). Development costs have also soared over the last decade, scrambling the economics of chip manufacturing. 

Intel has started selling chips using its embedded multi-die interconnect bridge, or EMIB, which made it possible to connect chiplets on a horizontal plane like puzzle pieces. EMIB is a small silicon bridge slipped in the package to establish a high-bandwidth pathway between chiplets. Intel uses EMIB inside its Stratix X FPGA and Kaby Lake G, which combines an Intel Core CPU and AMD Radeon GPU.

Last year, Intel introduced its Foveros chip stacking technology, which is used to connect chiplets in three dimensions. The layers are linked by electrical connections called through silicon vias, or TSVs. Intel's first Foveros chip, codenamed Lakefield, will start shipping before the end of 2019 with a 10-nanometer CPU stacked on top of a 22-nanometer die dedicated to analog, memory and other essential IP.

Intel is bringing together both types of advanced packaging with its new co-EMIB technology. The company said it can use co-EMIB to combine 3D-stacked Foveros chips in the same package using EMIB. The packaged chip performs basically the same as a monolithic die, according to Intel. The stacked chips can also be strapped to memory, analog and other tiles with high bandwidth and low power, according to Intel.

That makes Intel's co-EMIB technology ideal for high-performance server chips constrained by the physical limits of what can be manufactured on a monolithic die. Using chiplets could also cut costs. Smaller slices of silicon are less vulnerable to production defects, boosting yields. Even if there are imperfections in a chiplet, Intel can remove the faulty component and replace it with instead of having to discard the entire chipset.

Another advantage of advanced packaging is the ability to produce each slice of silicon on the process that suits it best. That could mean combining a 10-nanometer CPU, 14-nanometer I/O, 22-nanometer memory, 28-nanometer analog and 180-nanometer power management using Intel's co-EMIB. Chiplets can also be changed out to add or subtract features, curbing total costs and time-to-market.

That also lowers the bar for Intel to build custom chips using a library of chiplets. Customization is increasingly critical in areas like artificial intelligence jobs in data centers and Internet of Things devices, where general-purpose chips are seen as inadequate. Intel last year agreed to acquire Netspeed Systems, a startup that sells tools for combining various chips and memories more affordably.  

Intel said it would be able to assemble stacked chips in new ways with its Omni-Directional Interconnect, or ODI. The top chip in a stack can communicate horizontally with other chiplets in a way that resembles EMIB. But it also communicates over large vertical vias to the base silicon die sort of similar to Foveros. Intel's ODI technology also allows power delivery to the top chip from the base substrate.

Babak Sabi, general manager of assembly and test development at Intel, said the plan is "to develop leadership technology to connect chips and chiplets in a package to match the functionality of a monolithic system-on-chip." More advanced packaging could give Intel the "flexibility to mix and match IP blocks and process technologies with various memory and I/O elements in new device form factors."

Intel also debuted a die-to-die interface called Management Data Input/Output, or MDIO, which will be used to control communications between chiplets. The new protocol has better power efficiency and more than double the pin speed and bandwidth of the company's current advanced interface bus, or AIB, the central component of EMIB, the company said. Intel plans to start using MDIO sometime in 2020.

Other firms are also rallying around advanced packaging. TSMC, which has more than 450 customers globally, plans to start making chips using its SoIC chip stacking technology in 2021. AMD's latest line of server chips, codenamed Rome, uses CPU cores based on 7-nanometers from TSMC surrounding I/O based on 14-nanometers from Globalfoundries. The chips are linked over AMD's Infinity Fabric.

DARPA, part of the Department of Defense, is also trying to create chiplet standards. Those standards could serve as an alternative to the proprietary interconnects being pushed by Intel, TSMC and other firms using chiplets for internal use. The agency's CHIPS program aims to enable chiplets from any company to interface with any other company's chips, democratizing access to advanced packaging.

But Intel believes it has the upper hand in heterogeneous integration. In May, Murthy Redunchintala, Intel's chief engineering officer, said it should be able to offer "one Moore's Law of scaling" to customers at the start of every process node by doubling transistor density and "another Moore's Law of performance" at the end of the node by using advanced packaging and overhauling its architecture.

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