Registration is open for a series of SpeedWay Design Workshops featuring Avnet’s newly released ARTY Xilinx Artix-7 35T FPGA Evaluation Kit, the distributor announced this week.
The hands-on training session for engineers includes a full-day “Introduction to Vivado Design Suite” SpeedWay Workshop aimed at helping attendees accelerate their designs with Xilinx hardware description language (HDL). Using Xilinx Artix-7 hardware, attendees will learn techniques for entering, building, and debugging designs in Verilog or very high speed integrated circuit HDL (VHDL). They will also learn best practices in board planning, design creation, IP integration, design implementation and closure techniques, programming, and hardware debug using the Xilinx UltraFast™ Design Methodology, the distributor said.
“Avnet’s SpeedWay workshops are practical, hands-on trainings for designers who want to quickly learn a technology or skill,” said Jim Beneke, vice president of global technical marketing for Avnet Electronics Marketing. “Our new ‘Introduction to Vivado Design Suite’ course helps attendees learn the key elements of the Xilinx Vivado tools and apply the Xilinx UltraFast Design Methodology through the lab exercise targeting the new ARTY Evaluation Kit.”
The workshop also will help designers get up to speed on the ARTY board, MicroBlaze soft processor core, and the capabilities of the Artix-7 FPGAs. The workshops will be held in 35 cities throughout North America.
The Vivado workshop follows Avnet’s announcement last month that registration is open for its SmartFusion2 SpeedWay Design Workshop Series. Centered around the distributor’s new KickStart Kit that features Microsemi Corporation’s SmartFusion2 system-on-chip (SoC) FPGAs, the workshops will focus on the features of SmartFusion 2 flash-based devices, which use an ARM Cortex-M3 CPU and programmable logic, USB interface with a PC GUI, and Bluetooth low energy with an Android app.
Experts from Avnet and Microsemi will offer a mixture of lecture and hands-on labs covering the technology.
“The unique design of the SmartFusion2 SoC FPGA—mixing a hardened MCU block and FPGA on a single die—enables designers to maximize the functional resources common to many systems in minimal silicon space. At the same time, the FPGA fabric and firmware provide a great deal of flexibility for design customization,” said Stefan Rousseau, senior technical marketing engineer for Avnet. “These SpeedWay Design Workshops are designed to provide the tools, training and support designers need to leverage the many benefits of the SmartFusion2 technology and to streamline development of innovative, high-performance and secure IoT-enabled products.”
The workshops will be held in multiple cities this November.
